The present invention relates to digital computers, and in particular, to a mask generator for use in such computers.
It is common for masks to be used within the processor of digital computers. The masks are used, among other things, for removing or blanking out specified portions of binary micro-instructions or data words before such instructions or words are operated on by the processor. Masks are generally in the form of a binary word having either all logical "0's" or all logical "1's" in the inhibiting bits, i.e., the bits in the mask corresponding to the bits of the instruction or word which are to be removed or blanked out.
In the past, one method for generating masks has been to store a literal, i.e., a binary word having all its bits at a single logic level. A shifter is provided in the computer processor for receiving the literal and shifting the literal either to the left or right so that new bits brought in can be given a different logic level. The literal is shifted so that the new bits are equal in number to the number of bits which are to be masked from the micro-instruction or data word. After the desired number of new bits or inhibiting bits have been created, the modified literal is received by a rotator or multiplexer which rotates or aligns the inhibiting bits so that they appear at the proper location in the modified literal. The modified literal which has been shifted and rotated then becomes the mask and it is stored for used by the processor.
The disadvantage of this method is that it requires several cycles of processor time to shift and rotate the literal, time which could be used for other operations by the processor.
Another method for generating masks is to provide a file of stored masks, with every mask needed by the processor being stored in the file. The difficulty with this type of system is that oftentimes many different masks are needed during the operation of the processor, and that to store each needed mask would require an extremely large storage capacity. Such storage capacity is frequently expensive and would require space which could be used by other parts of the computer.
Still another approach for generating masks is that disclosed in U.S. Pat. No. 4,012,722, entitled "High Speed Modular Mask Generator," issued to Daniel D. Gajski et al. Two masks are used, one of which has logical 1's beginning at a bit location corresponding to the first bit of data to be passed without masking, and the other of which has logical 1's ending at the bit location corresponding to the last bit of data to be passed without masking. The two masks and the data to be masked are inputted to a set of AND gates. Each of two modular mask generators requires control signals for establishing the logic level of the output, in addition to the necessary address signal.